A typical ChISL document looks like this:
REG '0 = RegisterName: mode r § this is a inline comment default '0 § this is a multiline comment § REG '1 = AnotherRegister: § this register does nothing §
First of all note that ChISL is indentation sensitive. The following fragment is incorrect and would cause an error:
REG '0 = SomeRegister: mode r default '0 § !! ERROR: Indentation does not match !!
The only exception to this rule are multiline comments: They don’t have to adhere to the indentation rules. This freedom allows for nicely formatted ChISL documents.
The number format used by ChISL is as follows:
[bitlength]is the length of the number in bits. The bitlength is optional and defaults to one byte (8 bits).
[radix]numberidentifies the base of the number and the number itself. The radix is optional and defaults to decimal (
d). The radix can be one of the following:
Bfor a binary number, e.g.
Ofor an octal number, e.g.
Dfor a decimal number, e.g.
Hfor a hexadecimal number, e.g.
'0 § a decimal zero with 8 bit length. 16'0 § a 16 bit (2 byte) decimal zero. 4'b11 § the 4 bit long binary number `0011`. 32'hFFFF § the 32 bit hex number `0000FFFF`.
The register definition assign a name to a register and contains further detail such as mode, default value, and bit definitions.
REG number = name: body
The register body consists of a sequence of lines containing bit definitions, mode, and default.
Some interfaces use sub-indexing for addressing large registers. To accomodate this access method
the subregister (subindex) can be appended with a
REG register/subregister = name: body
A bit definition is either a one-line definition such as
BIT 3..0 = LowerBits
or a definition containing a body with further specification of the bit(s):
BIT 3..0 = LowerBits: mode r § these are the lower 4 bits of the register §
These two definitions give bits
0..3 the name
The general syntax for a bit definition is:
BIT [n..m|n] = name [§comment]| BIT [n..m|n] = name: body
body can contain
The legal modes are
Comments are preceded by the section sign
§. Comments can either be inline comments or multiline comments.
Inline comments run to the end of the line
mode rw § comment here!
Multiline comments run can span one ore more lines. Contrary to inline comments multiline comments
must be ended by a
§ A comment that spans several lines §
Simple register, no comments
0x00 obtains the name
Mode. It is a read-write register that has the default value
0x00. Bit 0 has the name
Flag1 and bit 1 has the has the name
Flag2. The other bits are unused.
REG 'h00 = Mode: mode rw default '0 BIT 0 = Flag1 § sets flag 1 BIT 1 = Flag2 § sets flag 2 BIT 2..7 = unused
Real register, with comments
The following is taken from the DW1000 CHISL file:
REG 'h00 = DEV_ID: § Device Identifier – includes device type and revision information § MODE r BIT 3..0 = REV: § Revision: This number will be updated for minor corrections and changes in operation § DEFAULT 4'h0 BIT 7..4 = VER: § Version: This number will be updated if a new version is produced that has significant differences from the previous version. § DEFAULT 4'h3 BIT 15..8 = MODEL: § The MODEL identifies the device. The DW1000 is device type 0x01. § DEFAULT 8'h01 BIT 31..16 = RIDTAG: § Register Identification Tag. It is planned that this will remain constant for all Decawave parts. The value is 0xDECA in hex. § DEFAULT 16'hDECA
As a varation fo the first example, here’s how the same would be defined for a register
0x00 with subindex
REG 'h00/'h04 = Mode_SubMode: mode rw default '0 BIT 0 = Flag3 § sets flag 3 BIT 1 = Flag4 § sets flag 4 BIT 2..7 = unused